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Modification of Constant Delay Logic: Design and Analysis

Alok Kumar Singh*, Preetisudha Meher

The review work on Constant Delay (CD) logic is presented in this paper. Dynamic (Complementary Metal Oxide Semiconductor) CMOS circuit style is introduced, allowing for a reduction in the number of transistors required to implement any logic. (Logical feeding) FTL avoids the use of more transistors in dynamic domino logic by implementing it with the same number of transistors as in dynamic logic. The CD logic generates high-speed operation of potential circuits. The timing window technique is examined, which is primarily used to reduce power dissipation, i.e., to shorten the evaluation time. CD logic has an unusual feature in that the output is pre-evaluated before the input from the previous stage is ready. This property provides a good performance analysis when compared to the dynamic and static logic styles. CD logic reduces charging current with the assistance of leakage current. Different circuits based on CD logic are analyzed for power, delay, (Power Delay Product) PDP, and noise calculation using 90 nm CMOS technology. The CD logic generates high-speed operation of potential circuits. The timing window width technique is examined in order to reduce circuit power consumption while maintaining circuit performance speed. Using 90 nm GPDK CMOS technology, the proposed logic has a much higher average speed than previous works.